The present invention relates generally to frequency synthesis schemes, and more particularly to a frequency synthesis scheme performed entirely inside a field programmable gate array (FPGA).
Phase locked loops (PLLs) are used in various applications such as frequency synthesis, tone decoding, demodulation of AM and FM signals, pulse synchronization of signals from noisy sources (e.g., magnetic tapes), and regeneration of xe2x80x9ccleanxe2x80x9d signals. A PLL typically includes the following components: a phase detector, low-pass filter, amplifier, and voltage-controlled oscillator (VCO). In frequency synthesis applications, a divide-by-n counter is added between the VCO output and the phase detector in the PLL loop. The phase detector compares two input frequencies: fin which is the frequency of an input or reference signal and fVCO which is the frequency of the signal generated by the VCO. If fin does not equal fVCO, then the phase detector generates a phase-error signal which is then filtered by the low-pass filter and amplified by the amplifier. The phase-error signal is received by the VCO and causes the frequency of the VCO output signal to deviate to the value of fin. It is further noted that the phase detector converts phase to voltage and that the VCO converts voltage to the time derivative of phase (i.e., frequency). When the fVCO value becomes equal to the fin value, the VCO will quickly xe2x80x9clockxe2x80x9d to the fin value, thus maintaining a fixed phase relationship with the input signal.
In frequency synthesis applications, the PLL generates an output signal that is an integer multiple n of the input frequency fin. The integer multiple n can be digitally adjusted, resulting in a flexible signal source that can be controlled by, for example, a computer.
In another field of technology, there exists programmable devices which are a class of general-purpose chips that can be configured for a wide variety of applications. One type of programmable device is commonly known as the field programmable gate array (FPGA). The interconnects between all the elements in an FPGA are designed to be user programmable.
Presently, there are four main types of FPGAs that are commercially available: symmetrical array, row-based, hierarchical PLD, and sea-of-gates. FPGAs provide the benefits of custom CMOS VLSI, while avoiding the initial cost, time delay, and inherent risks of a conventional masked gate array. FPGAs are customized by loading configuration data into the internal memory cells. An FPGA can either actively read its configuration data out of an external serial PROM or byte-parallel PROM (master mode), or the configuration data can be written into the FPGA (slave and peripheral mode). Where the FPGA is used in a Reconfigurable Computing Platform, particularly those using systems, methods, and/or apparatuses according to, e.g., U.S. Pat. Nos. 5,933,642, 5,854,918, 5,805,871, and 5,794,062, the FPGA device which performs computational operations is designed using a Hardware Description Language (HDL).
The FPGA design process is separate from the use of the FPGA as a computational element with stored programs, and typically results in a downloadable bitstream file (i.e., the circuit design) for dynamic configuration of the FPGA at runtime. Control over configuration at runtime in the FPGA is done with stored programs, which are separate binary data (xe2x80x9csoftwarexe2x80x9d) that are linked with bitstream data (xe2x80x9chardwarexe2x80x9d). These programs are generally sequences of instructions that have been compiled by a compiler for a High Level Language such as xe2x80x9cCxe2x80x9d, with the inclusion of bitstream data for the FPGA primarily a linking step in the compilation. Through these particular methods, xe2x80x9chardwarexe2x80x9d, i.e., the selection of an operational computer to execute programs, becomes a library for use by those programs. The FPGA is hence configured from within an application program at runtime. FPGAs can be programmed in an unlimited number of times and can support system clock rates of up to 300 megahertz with silicon technology of the year 2000.
The above-mentioned approaches do not disclose or suggest integrating a frequency synthesis scheme entirely inside an FPGA. Furthermore, the above-mentioned approaches do not disclose or suggest constructing an entire PLL in an FPGA.
The present invention broadly provides an apparatus and method for performing phase-lock in a field programmable gate array. In one embodiment of the invention, the apparatus includes a phase detector configured to determine a phase difference between a carry logic oscillator signal and a reference clock signal; and a combinational circuit coupled to the phase detector, and adapted to function as a variable carry logic oscillator, and further configured to generate the carry logic oscillator signal.
In another embodiment, the present invention provides an apparatus for performing phase-lock in a field programmable gate array, including a phase detector configured to determine a phase difference between a carry logic oscillator signal and a reference clock signal; and a carry logic oscillator coupled to the phase detector and configured to generate the carry logic oscillator signal. The carry logic oscillator includes a first column of carry logic cells and a second column of carry logic cells coupled together by a feedback loop for enabling quadrature phasing. The carry logic oscillator further includes a logic gate coupled to the first column and the second column, and the logic gate enables a frequency multiplication function.
The present invention further provides a method for performing phase-lock in a field programmable gate array. In one embodiment, the method includes: using a carry logic oscillator in a field programmable gate array to generate a carry logic oscillator signal; and determining a phase difference between the carry logic oscillator signal and a reference clock signal. The present invention makes possible the following advantages. The present invention can be directly implemented on-chip in an FPGA, without use of analog parts for synchronization, signaling, and transmission. Additionally, no special on-chip circuits are required for the present invention. Additionally, no external components (i.e., outside the FPGA) are required to implement the present invention.